The performance of a computing system is vitally affected by the speed and accuracy with which arithmetic operations are performed. This is because many of the instructions executed by the computer require arithmetic operation. Arithmetic circuitry is often the most complex circuitry in the instruction execution unit of a computer in terms of the number of gates and logic levels. Therefore, arithmetic operations tend to be slow and prone to error. One important aspect of the result of arithmetic operations is the determination of condition codes.
A condition code is set by a computer to reflect the outcome of an arithmetic operation. This code assists the computer in making operational decisions which depend upon arithmetic results. Condition codes are also important in some non-arithmetic operations, such as data loading instructions involving generating data complements. It is desirable, for performance reasons, to compute a condition code concurrently with the execution of the operation on whose outcome the state of the code depends.
Typically, the condition code is employed to indicate that the result of an operation is greater than zero (GT), less than zero (LT), or equal to zero (EQ). LT is the easiest outcome to detect, because it simply involves examining the sign bit of the result. In general, GT and EQ are more difficult outcomes to detect, because the sign bit of the result is set positive when the result is either zero or a positive quantity. Therefore, examining the sign bit of the result, when the result is equal to zero, does not indicate whether the result is zero or a positive number. However, for the result of a specific instruction on specific data, EQ and GT are mutually exclusive. Thus, determining one is sufficient for the determination of the other, once LT has been excluded.
In adder operations, the traditional method of determining the RESULT=0 (EQ) condition is to NOR all the output bits of an adder circuit in the arithmetic/logic unit (ALU). However, since many architectures require 32-bit data paths for fixed point units, they also require adders of 32 bits in width. Thus, this NORing of bits will require at least two additional stages of logic, depending on the technology used for implementation. As a higher demand is placed on improvements of cycle time, the addition of stages to an adder circuit can force the condition path to become critical, therefore pushing its computation into the next machine cycle. It is evident that early computation of the greater than zero condition will enhance the operational speed of a computer. The inventors have made the critical observation that the GT condition can be detected by the early elimination of the EQ and LT conditions.